Constraint Centric Scheduling Guide

The advent of architectures with software-exposed resources (Spatial Architectures) has created a demand for universally applicable scheduling techniques. This paper describes our generalized spatial scheduling framework, formulated with Integer Linear Programming, and specifically accomplishes two goals. First, using the ?Simple? architecture, it illustrates how to use our open-source tool to create a customized scheduler and covers problem formulation with ILP and GAMS. Second, it summarizes results on the application to three real architectures (TRIPS,DySER,PLUG), demonstrating the technique?s practicality and competitiveness with existing schedulers

Mechanisms for Parallelism Specialization for the DySER Architecture

Specialization is a promising direction for improving processor energy efficiency. With functionality specialization, hardware is designed for application-specific units of computation. With parallelism specialization, hardware is designed to exploit abundant data-level parallelism. The hardware for these specialization approaches have similarities including many functional units and the elimination of per-instruction overheads. Even so, previous architectures have focused on only one form of specialization. Our goal is to develop mechanisms that unify these two approaches into a single architecture. We develop the DySER architecture to support both, by Dynamically Specializing Execution Resources to match program regions. By dynamically specializing frequently executing regions, and applying a set of judiciously chosen parallelism mechanisms--namely region growing, vectorized communication, and region virtualization--we show DySER provides efficient functionality and parallelism specialization. It outperforms an OOO-CPU, SSE-acceleration, and GPU-acceleration by up to 4.1x, 4.7x and 4x respectively, while consuming 9%, 86%, and 8% less energy. Our full-system FPGA prototype of DySER integrated into OpenSPARC demonstrates an implementation is practical

Studying Hybrid Von-Neumann/Dataflow Execution Models

Hardware specialization is becoming a promising paradigm for future microprocessors. Unfortunately, by its very nature, the exploration of specialization ideas, (the artifact is dubbed an ?accelerator?) are developed, evaluated, and published as end-to-end vertical silos spanning application, language/compiler, and hardware architecture, with per-accelerator customized tools, and little opportunity for cross-application of ideas from one accelerator into another. This paper develops a novel program representation suitable for the hardware specialization paradigm, called the transformable dependence graph (TDG), which combines semantic information about program properties and low-level hardware events (cache misses, branch mis-predictions, resource hazards, energy expended by hardware events) in a single representation. We demonstrate that the TDG is a feasible, simple, and accurate modeling technique for transparent specialization approaches, enabling architectures to be compared and analyzed easily in a single framework. We demonstrate models for four previously proposed accelerators